View A1020B_1659851.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

april 1996 1-283 ? 1996 actel corporation act ? 1 series fpgas features ? 5v and 3.3v families fully compatible with jedec specifications ? up to 2000 gate array gates (6000 pld equivalent gates) ? replaces up to 50 ttl packages ? replaces up to twenty 20-pin pal ? packages ? design library with over 250 macro functions ? gate array architecture allows completely automatic place and route ? up to 547 programmable logic modules ? up to 273 flip-flops ? data rates to 75 mhz ? two in-circuit diagnostic probe pins support speed analysis to 25 mhz ? built-in high speed clock distribution network ? i/o drive to 10 ma (5 v), 6 ma (3.3 v) ? nonvolatile, user programmable ? fabricated in 1.0 micron cmos technology description the act? 1 series of field programmable gate arrays (fpgas) offers a variety of package, speed, and application combinations. devices are implemented in silicon gate, 1-micron two-level metal cmos, and they employ actels plice ? antifuse technology. the unique architecture offers gate array flexibility, high performance, and instant turnaround through user programming. device utilization is typically 95 to 100 percent of available logic modules. act 1 devices also provide system designers with unique on-chip diagnostic probe capabilities, allowing convenient testing and debugging. additional features include an on-chip clock driver with a hardwired distribution network. the network provides efficient clock distribution with minimum skew. the user-definable i/os are capable of driving at both ttl and cmos drive levels. available packages include plastic and ceramic j-leaded chip carriers, ceramic and plastic quad flatpacks, and ceramic pin grid array. a security fuse may be programmed to disable all further programming and to protect the design from being copied or reverse engineered. product family profile the designer and designer advantage? systems the act 1 device family is supported by actels designer and designer advantage systems, allowing logic design implementation with minimum effort. the systems offer microsoft ? windows ? and x windows ? graphical user interfaces and integrate with the resident cae system to provide a complete gate array design environment: schematic capture, simulation, fully automatic place and route, timing verification, and device programming. the systems also include the actmap ? vhdl optimization and synthesis tool and the actgen ? macro builder, a powerful macro function generator for counters, adders, and other structural blocks. device a1010b a10v10b A1020B a10v20b capacity gate array equivalent gates pld equivalent gates ttl equivalent packages 20-pin pal equivalent packages 1,200 3,000 30 12 2,000 6,000 50 20 logic modules 295 547 flip-flops (maximum) 147 273 routing resources horizontal tracks/channel vertical tracks/column plice antifuse elements 22 13 112,000 22 13 186,000 user i/os (maximum) 57 69 packages: 44 plcc 68 plcc 100 pqfp 80 vqfp 84 cpga 44 plcc 68 plcc 84 plcc 100 pqfp 80 vqfp 84 cpga 84 cqfp performance 5 v data rate (maximum) 3.3 v data rate (maximum) 75 mhz 55 mhz 75 mhz 55 mhz note: see product plan on page 1-286 for package availability.
1- 284 the systems are available for 386/486/pentium ? pc and for hp ? and sun ? workstations and for running viewlogic ? , mentor graphics ? , cadence ? , orcad ? , and synopsys design environments. act 1 device structure a partial view of an act 1 device ( figure 1 ) depicts four logic modules and distributed horizontal and vertical interconnect tracks. plice antifuses, located at intersections of the horizontal and vertical tracks, connect logic module inputs and outputs. during programming, these antifuses are addressed and programmed to make the connections required by the circuit application. the act 1 logic module the act 1 logic module is an 8-input, one-output logic circuit chosen for the wide range of functions it implements and for its efficient use of interconnect routing resources ( figure 2 ). the logic module can implement the four basic logic functions (nand, and, or, and nor) in gates of two, three, or four inputs. each function may have many versions, with different combinations of active-low inputs. the logic module can also implement a variety of d-latches, exclusivity functions, and-ors, and or-ands. no dedicated hardwired latches or flip-flops are required in the array, since latches and flip-flops may be constructed from logic modules wherever needed in the application. i/o buffers each i/o pin is available as an input, output, three-state, or bidirectional buffer. input and output levels are compatible with standard ttl and cmos specifications. outputs sink or figure 1 ? partial view of an act 1 device figure 2 ? act 1 logic module
1- 285 act ? 1 series fpgas source 10 ma at ttl levels. see electrical specifications for additional i/o buffer specifications. device organization act 1 devices consist of a matrix of logic modules arranged in rows separated by wiring channels. this array is surrounded by a ring of peripheral circuits including i/o buffers, testability circuits, and diagnostic probe circuits providing real-time diagnostic capability. between rows of logic modules are routing channels containing sets of segmented metal tracks with plice antifuses. each channel has 22 signal tracks. vertical routing is permitted via 13 vertical tracks per logic module column. the resulting network allows arbitrary and flexible interconnections between logic modules and i/o modules. probe pin act 1 devices have two independent diagnostic probe pins. these pins allow the user to observe any two internal signals by entering the appropriate net name in the diagnostic software. signals may be viewed on a logic analyzer using actels actionprobe ? diagnostic tools. the probe pins can also be used as user-defined i/os when debugging is finished. act 1 array performance temperature and voltage effects worst-case delays for act 1 arrays are calculated in the same manner as for masked array products. a typical delay parameter is multiplied by a derating factor to account for temperature, voltage, and processing effects. however, in an act 1 array, temperature and voltage effects are less dramatic than with masked devices. the electrical characteristics of module interconnections on act 1 devices remain constant over voltage and temperature fluctuations. as a result, the total derating factor from typical to worst-case for a standard speed act 1 array is only 1.19 to 1, compared to 2 to 1 for a masked gate array. logic module size logic module size also affects performance. a mask programmed gate array cell with four transistors usually implements only one logic level. in the more complex logic module (similar to the complexity of a gate array macro) of an act 1 array, implementation of multiple logic levels within a single module is possible. this eliminates interlevel wiring and associated rc delays. the effect is termed net compression. ordering information application (t emper ature range) c = commercial (0 to +70 c) i = industr ial (C40 to +85 c) m = militar y (C55 to +125 c) b = mil-std-883 p ac kage t ype pl = plastic j-leaded chip carr iers pq = plastic quad flatpac ks cq = cer amic quad flatpac k pg = cer amic pin gr id arr a y vq = v er y thin quad flatpac k speed gr ade blank = standard speed C1 = appro ximately 15% f aster than standard C2 = appro ximately 25% f aster than standard C3 = appro ximately 35% f aster than standard p ar t number a1010 = 1200 gates (5 v) a1020 = 2000 gates (5 v) a10v10 = 1200 gates (3.3 v) a10v20 = 2000 gates (3.3 v) die re vision b = 1.0 micron cmos process p ac kage lead count a1010 b C 2 pl 84 c
1- 286 product plan speed grade* application std C1 C2 C3 c i m b a1010b de vice 44-pin plastic leaded chip carr ier (pl) 68-pin plastic leaded chip carr ier (pl) 100-pin plastic quad flatpac k (pq) 80-pin v er y thin (1.0 mm) quad flatpac k (vq) 84-pin cer amic pin gr id arr a y (pg) 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 A1020B de vice 44-pin plastic leaded chip carr ier (pl) 68-pin plastic leaded chip carr ier (pl) 84-pin plastic leaded chip carr ier (pl) 100-pin plastic quad flatpac k (pq) 80-pin v er y thin (1.0 mm) quad flatpac k (vq) 84-pin cer amic pin gr id arr a y (pg) 84-pin cer amic quad flatpac k (cq) 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 a10v10b de vice 68-pin plastic leaded chip carr ier (pl) 80-pin v er y thin (1.0 mm) quad flatpac k (vq) 4 4 4 4 a10v20b de vice 68-pin plastic leaded chip carr ier (pl) 84-pin plastic leaded chip carr ier (pl) 80-pin v er y thin (1.0 mm) quad flatpac k (vq) 4 4 4 4 4 4 applications: c = commercial a v ailability: 4 = a v ailab le * speed gr ade: C1 = appro x. 15% f aster than standard i = industr ial p = planned C2 = appro x. 25% f aster than standard m = militar y = not planned C3 = appro x. 35% f aster than standard b = mil-std-883 device resources user i/os de vice logic modules gates 44-pin 68-pin 80-pin 84-pin 100-pin a1010b , a10v10b 295 1200 34 57 57 57 57 A1020B , a10v20b 547 2000 34 57 69 69 69
1- 287 act ? 1 series fpgas pin description clk clock (input) ttl clock input for global clock distribution network. the clock input is buffered prior to clocking the logic modules. this pin can also be used as an i/o. dclk diagnostic clock (input) ttl clock input for diagnostic probe and device programming. dclk is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. gnd gr ound input low supply voltage. i/o input/output (input, output) i/o pin functions as an input, output, three-state, or bidirectional buffer. input and output levels are compatible with standard ttl and cmos specifications. unused i/o pins are automatically driven low by the als software. mode mode (input) the mode pin controls the use of multifunction pins (dclk, pra, prb, sdi). when the mode pin is high, the special functions are active. when the mode pin is low, the pins function as i/o. to provide actionprobe capability, the mode pin should be terminated to gnd through a 10k resistor so that the mode pin can be pulled high when required. nc no connection this pin is not connected to circuitry within the device. absolute maximum ratings 1 free air temperature range pra pr obe a (output) the probe a pin is used to output data from any user-defined design node within the device. this independent diagnostic pin is used in conjunction with the probe b pin to allow real-time diagnostic output of any signal path within the device. the probe a pin can be used as a user-defined i/o when debugging has been completed. the pins probe capabilities can be permanently disabled to protect the programmed designs confidentiality. pra is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. prb pr obe b (output) the probe b pin is used to output data from any user-defined design node within the device. this independent diagnostic pin is used in conjunction with the probe a pin to allow real-time diagnostic output of any signal path within the device. the probe b pin can be used as a user-defined i/o when debugging has been completed. the pins probe capabilities can be permanently disabled to protect the programmed designs confidentiality. prb is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. sdi serial data input (input) serial data input for diagnostic probe and device programming. sdi is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. v cc supply v oltage input high supply voltage. recommended operating conditions symbol p arameter limits units v cc dc supply v oltage 2 C0.5 to +7.0 v olts v i input v oltage C0.5 to v cc +0.5 v olts v o output v oltage C0.5 to v cc +0.5 v olts i io i/o sink/source current 3 20 ma t stg stor age t emper ature C65 to +150 c notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. device should not be operated outside the recommended operating conditions. 2. v pp = v cc , except during device programming. 3. device inputs are normally high impedance and draw extremely low current. however, when input voltage is greater than v cc + 0.5 v or less than gnd C 0.5 v, the internal protection diode will be forward biased and can draw excessive current. p arameter commer cial industrial militar y units t emper ature range 1 0 to +70 C40 to +85 C55 to +125 c p o w er supply t oler ance 5 10 10 %v cc note: 1. ambient temperature (t a ) used for commercial and industrial; case temperature (t c ) used for military.
1- 288 electrical specifications (5v) symbol p arameter commer cial industrial militar y units min. max. min. max. min. max. v oh 1 (i oh = C10 ma) 2 2.4 v (i oh = C6 ma) 3.84 v (i oh = C4 ma) 3.7 3.7 v v ol 1 (i ol = 10 ma) 2 0.5 v (i ol = 6 ma) 0.33 0.40 0.40 v v il C0.3 0.8 C0.3 0.8 C0.3 0.8 v v ih 2.0 v cc + 0.3 2.0 v cc + 0.3 2.0 v cc + 0.3 v input t r ansition time t r , t f 2 500 500 500 ns c io i/o capacitance 2, 3 10 10 10 pf standb y current, i cc 4 (typical = 1 ma) 3 10 20 ma leakage current 5 C10 10 C10 10 C10 10 m a notes: 1. only one output tested at a time. v cc = min. 2. not tested, for information only. 3. includes worst-case 84-pin plcc package capacitance. v out = 0 v, f = 1 mhz. 4. typical standby current = 1 ma. all outputs unloaded. all inputs = v cc or gnd. 5. v o , v in = v cc or gnd. electrical specifications (3.3v) p arameter commer cial units min. max. v oh 1 (i oh = C4 ma) 2.15 v (i oh = C3.2 ma) 2.4 v v ol 1 (i ol = 6 ma) 0.4 v v il C0.3 0.8 v v ih 2.0 v cc + 0.3 v input t r ansition time t r , t f 2 500 ns c io i/o capacitance 2, 3 10 pf standb y current, i cc 4 (typical = 0.3 ma) 0.75 ma leakage current 5 C10 10 m a notes: 1. only one output tested at a time. v cc = min. 2. not tested, for information only. 3. includes worst-case 84-pin plcc package capacitance. v out = 0 v, f = 1 mhz. 4. typical standby current = 0.3 ma. all outputs unloaded. all inputs = v cc or gnd. 5. v o , v in = v cc or gnd
1- 289 act ? 1 series fpgas package thermal characteristics the device junction to case thermal characteristics is q jc, and the junction to ambient air characteristics is q ja. the thermal characteristics for q ja are shown with two different air flow rates. maximum junction temperature is 150 c. a sample calculation of the maximum power dissipation for an 84-pin plastic leaded chip carrier at commercial temperature is as follows: general power equation p = [i cc standby + i cc active] * v cc + i ol * v ol * n + i oh * (v cc C v oh ) * m where: i cc standby is the current flowing when no inputs or outputs are changing. i cc active is the current flowing due to cmos switching. i ol , i oh are ttl sink/source currents. v ol , v oh are ttl level output voltages. n equals the number of outputs driving ttl loads to v ol . m equals the number of outputs driving ttl loads to v oh . an accurate determination of n and m is problematical because their values depend on the family type, design details, and on the system i/o. the power can be divided into two components: static and active. static power component actel fpgas have small static power components that result in lower power dissipation than pals or plds. by integrating multiple pals/plds into one fpga, an even greater reduction in board-level power dissipation can be achieved. the power due to standby current is typically a small component of the overall power. standby power is calculated below for commercial, worst case conditions. i cc v cc power 3 ma 5.25 v 15.75 mw (max) 1 ma 5.25 v 5.25 mw (typ) 0.75 ma 3.60 v 2.70 mw (max) 0.30 ma 3.30 v 0.99 mw (typ) active power component power dissipation in cmos devices is usually dominated by the active (dynamic) power dissipation. this component is frequency dependent, a function of the logic and the external i/o. active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to pc board traces and load device inputs. an additional component of the active power dissipation is the totem-pole current in cmos transistor pairs. the net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. p ac ka g e t ype pin count q jc q ja still air q ja 300 ft/min units plastic j-leaded chip carr ier 44 68 84 15 13 12 45 38 37 35 29 28 c/w c/w c/w plastic quad flatpac k 100 13 48 40 c/w v er y thin (1.0 mm) quad flatpac k 80 12 43 35 c/w cer amic pin gr id arr a y 84 8 33 20 c/w cer amic quad flatpac k 84 5 40 30 c/w m a x j u n c t i o n t e m p . c ( ) m a x c o m m e r c i a l t e m p . c ( ) C q j a c w ( ) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 150 c 70 c C 37 c w - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2.2 w = =
1- 290 equivalent capacitance the power dissipated by a cmos circuit can be expressed by the equation 1. power (uw) = c eq * v cc2 * f (1) where: c eq is the equivalent capacitance expressed in pf. v cc is the power supply in volts. f is the switching frequency in mhz. equivalent capacitance is calculated by measuring i cc active at a specified frequency and voltage for each circuit component of interest. measurements have been made over a range of frequencies at a fixed value of v cc . equivalent capacitance is frequency independent so that the results may be used over a wide range of operating conditions. equivalent capacitance values are shown below. c eq values for actel fpgas to calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. equation 2 shows a piece-wise linear summation over all components. power = v cc 2 * [(m * c eqm * f m ) modules + (n * c eqi * f n ) inputs + (p * (c eqo + c l ) * f p ) outputs + 0.5 * (q 1 * c eqcr * f q1 ) routed_clk1 + (r 1 * f q1 ) routed_clk1 ] (2) where: fixed capacitance values for actel fpgas (pf) r 1 device type routed_clk1 a1010b 41.4 A1020B 68.6 a10v10b 40 a10v20b 65 determining average switching frequency to determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. the following guidelines are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. these guidelines are as follows: a10v10b a10v20b a1010b A1020B modules (c eqm ) 3.2 3.7 input buffers ( ceqi ) 10.9 22.1 output buffers (c eqo ) 11.6 31.2 routed array clock buffer loads (c eqcr ) 4.1 4.6 m = number of logic modules switching at fm n = number of input buffers switching at fn p = number of output buffers switching at fp q 1 = number of clock loads on the first routed array clock (all families) r 1 = fixed capacitance due to first routed array clock (all families) c eqm = equivalent capacitance of logic modules in pf c eqi = equivalent capacitance of input buffers in pf c eqo = equivalent capacitance of output buffers in pf c eqcr = equivalent capacitance of routed array clock in pf c l = output lead capacitance in pf f m = average logic module switching rate in mhz f n = average input buffer switching rate in mhz f p = average output buffer switching rate in mhz f q1 = average first routed array clock rate in mhz (all families) logic modules (m) 90% of modules inputs switching (n) #inputs/4 outputs switching (p) #outputs/4 first routed array clock loads (q 1 ) 40% of modules load capacitance (c l ) 35 pf average logic module switching rate (f m ) f/10 average input switching rate (f n ) f/5 average output switching rate (f p ) f/10 average first routed array clock rate (f q1 ) f
1- 291 act ? 1 series fpgas functional timing tests ac timing for logic module internal delays is determined after place and route. the directtime analyzer utility displays actual timing parameters for circuit delays. act 1 devices are ac tested to a binning circuit specification. the circuit consists of one input buffer + n logic modules + one output buffer (n = 16 for a1010b; n = 28 for A1020B). the logic modules are distributed along two sides of the device, as inverting or non-inverting buffers. the modules are connected through programmed antifuses with typical capacitive loading. propagation delay [t pd = (t plh + t phl )/2] is tested to the following ac test specifications. output buffer performance derating (5v) note: the above curves are based on characterizations of sample devices and are not completely tested on all devices. output buffer performance derating (3.3v) note: the above curves are based on characterizations of sample devices and are not completely tested on all devices. sink 12 10 8 6 4 0.2 0.3 0.4 0.5 0.6 v ol (v olts) i ol (ma) sour ce C4 C6 C8 C10 C12 4.0 3.6 3.2 2.8 2.4 v oh (v olts) i oh (ma) 2.0 militar y , w orst-case v alues at 125 c , 4.5 v . commercial, w orst-case v alues at 70 c , 4.75 v . sink 12 10 8 6 4 0.0 0.1 0.2 0.3 0.4 v ol (v olts) i ol (ma) sour ce C4 C6 C8 C10 C12 0 0.5 1.0 1.5 2.0 v oh (v olts) i oh (ma) 2.5 commercial, w orst-case v alues at 70 c , 4.75 v .
1- 292 act 1 timing module* predictable performance: tight delay distributions propagation delay between logic modules depends on the resistive and capacitive loading of the routing tracks, the interconnect elements, and the module inputs being driven. propagation delay increases as the length of routing tracks, the number of interconnect elements, or the number of inputs increases. from a design perspective, the propagation delay can be statistically correlated or modeled by the fanout (number of loads) driven by a module. higher fanout usually requires some paths to have longer routing tracks. the act 1 family delivers a very tight fanout delay distribution. this tight distribution is achieved in two ways: by decreasing the delay of the interconnect elements and by decreasing the number of interconnect elements per path. actels patented plice antifuse offers a very low resistive/capacitive interconnect. the act 1 familys antifuses, fabricated in 1.0 micron lithography, offer nominal levels of 200 ohms resistance and 7.5 femtofarad (ff) capacitance per antifuse. the act 1 fanout distribution is also tight due to the low number of antifuses required for each interconnect path. the act 1 familys proprietary architecture limits the number of antifuses per path to a maximum of four, with 90% of interconnects using two antifuses. timing characteristics timing characteristics for act 1 devices fall into three categories: family dependent, device dependent, and design dependent. the input and output buffer characteristics are common to all act 1 family members. internal routing delays are device dependent. design dependency means actual delays are not determined until after placement and routing of the user design is complete. delay values may then be determined by using the directtime analyzer utility or performing simulation with post-layout delays. critical nets and typical nets propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. critical net delays can then be applied to the most time-critical paths. critical nets are determined by net property assignment prior to placement and routing. up to 6% of the nets in a design may be designated as critical, while 90% of the nets in a design are typical. long tracks some nets in the design use long tracks. long tracks are special routing resources that span multiple rows, columns, or modules. long tracks employ three and sometimes four antifuse connections. this increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. typically, up to 6% of nets in a fully utilized device require long tracks. long tracks contribute approximately 5 ns to 10 ns delay. this additional delay is represented statistically in higher fanout (fo=8) routing delays in the data sheet specifications section. * values shown for act 1 C3 speed devices at worst-case commercial conditions. output dela y input dela y i/o module t inyl = 3.1 ns t ird2 = 1.4 ns logic module t pd = 2.9 ns i/o module t rd1 = 0.9 ns t dlh = 6.7 ns arra y clock f max = 70 mhz t rd4 = 3.1 ns t rd8 = 6.6 ns predicted routing dela ys t ckh = 5.6 ns fo = 128 t ird1 = 0.9 ns t ird4 = 3.1 ns t ird8 = 6.6 ns t co = 2.9 ns t enhz = 11.6 ns t rd2 = 1.4 ns internal dela ys
1- 293 act ? 1 series fpgas timing derating a best case timing derating factor of 0.45 is used to reflect best case processing. note that this factor is relative to the standard speed timing parameters, and must be multiplied by the appropriate voltage and temperature derating factors for a given application. timing derating factor (temperature and voltage) industrial militar y min. max. min. max. (commercial minim um/maxim um speci? cation) x 0.69 1.11 0.67 1.23 timing derating factor for designs at typical temperature (t j = 25 c) and voltage (5.0 v) (commercial maxim um speci? cation) x 0.85 temperature and voltage derating factors (normalized to worst-case commercial, t j = 4.75 v, 70 c) C55 C40 0 25 70 85 125 4.50 0.75 0.79 0.86 0.92 1.06 1.11 1.23 4.75 0.71 0.75 0.82 0.87 1.00 1.05 1.16 5.00 0.69 0.72 0.80 0.85 0.97 1.02 1.13 5.25 0.68 0.69 0.77 0.82 0.95 0.98 1.09 5.50 0.67 0.69 0.76 0.81 0.93 0.97 1.08 note: this derating factor applies to all routing and propagation delays. 0 . 6 0 . 7 0 . 8 0 . 9 1 . 0 1 . 1 1 . 2 1 . 3 4 . 5 0 4 . 7 5 5 . 0 0 5 . 2 5 5 . 5 0 d e r a t i n g f a c t o r v o l t a g e ( v ) 1 2 5 c 8 5 c 7 0 c 2 5 c 0 c 4 0 c 5 5 c j unction t emperature and v olta g e derating cur ves (normaliz ed to w or st-case commer cial, t j = 4.75 v , 70 c)
1- 294 temperature and voltage derating factors (normalized to worst-case commercial, t j = 3.0 v, 70 c) 0 25 70 2.7 1.05 1.09 1.30 3.0 0.81 0.84 1.00 3.3 0.64 0.67 0.79 3.6 0.62 0.64 0.76 note: this derating factor applies to all routing and propagation delays. j unction t emperature and v olta g e derating cur ves (normaliz ed to w or st-case commer cial, t j = 3.0 v , 70 c) 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.5 2.7 3.0 3.3 3.6 derating f actor v olta g e (v) 0.6 0 c 25 c 70 c
1- 295 act ? 1 series fpgas parameter measurement output buffer delays ac test loads input buffer delays module delays t o a c test loads (sho wn belo w) p ad d e trib uff in v cc gnd 50% p ad v ol v oh 1.5 v t dlh 50% 1.5 v t dhl e v cc gnd 50% p ad v ol 1.5 v t enzl 50% 10% t enlz e v cc gnd 50% p ad gnd v oh 1.5 v t enzh 50% 90% t enhz v cc load 1 (used to measure pr opa gation dela y) load 2 (used to measure rising/falling edg es) 35 pf t o the output under test v cc gnd 35 pf t o the output under test r to v cc f or t plz /t pzl r to gnd f or t phz /t pzh r = 1 k w p ad y inb uf p ad 3 v 0 v 1.5 v y gnd v cc 50% t inyh 1.5 v 50% t inyl s a b y s , a or b out gnd v cc 50% t plh out gnd gnd v cc 50% 50% 50% v cc 50% 50% t phl t phl t plh
1- 296 sequential timing characteristics flip-flops and latches note: d represents all data functions involving a, b, s for multiplexed flip-flops. (p ositiv e edge tr iggered) d e clk clr pre q d 1 clk e q pre, clr t wclka t w asyn t hd t suena t sud t rs t a t co
1- 297 act ? 1 series fpgas act 1 timing characteristics (worst-case commercial conditions, v cc = 4.75 v, t j = 70 c) 1 logic module pr opa gation dela ys C3 speed C2 speed C1 speed std speed 3.3 v speed p arameter description min. max. min. max. min. max. min. max. min. max. units t pd1 single module 2.9 3.4 3.8 4.5 6.5 ns t pd2 dual module macros 6.8 7.8 8.8 10.4 15.1 ns t co sequential clk to q 2.9 3.4 3.8 4.5 6.5 ns t go latch g to q 2.9 3.4 3.8 4.5 6.5 ns t rs flip-flop (latch) reset to q 2.9 3.4 3.8 4.5 6.5 ns predicted routing dela ys 2 t rd1 fo=1 routing dela y 0.9 1.1 1.2 1.4 2.0 ns t rd2 fo=2 routing dela y 1.4 1.7 1.9 2.2 3.2 ns t rd3 fo=3 routing dela y 2.1 2.5 2.8 3.3 4.8 ns t rd4 fo=4 routing dela y 3.1 3.6 4.1 4.8 7.0 ns t rd8 fo=8 routing dela y 6.6 7.7 8.7 10.2 14.8 ns sequential timing characteristics 3 t sud flip-flop (latch) data input setup 5.5 6.4 7.2 8.5 10.0 ns t hd 4 flip-flop (latch) data input hold 0.0 0.0 0.0 0.0 0.0 ns t suena flip-flop (latch) enab le setup 5.5 6.4 7.2 8.5 10.0 ns t hena flip-flop (latch) enab le hold 0.0 0.0 0.0 0.0 0.0 ns t wclka flip-flop (latch) cloc k activ e pulse width 6.8 8.0 9.0 10.5 9.8 ns t w asyn flip-flop (latch) asynchronous pulse width 6.8 8.0 9.0 10.5 9.8 ns t a flip-flop cloc k input p er iod 14.2 16.7 18.9 22.3 20.0 ns f max flip-flop (latch) cloc k f requency (fo = 128) 70 60 53 45 50 mhz notes: 1. v cc = 3.0 v for 3.3v specifications. 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating d evice performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timi ng is based on actual routing delay measurements performed on the device prior to shipment. 3. setup times assume fanout of 3. further testing information can be obtained from the directtime analyzer utility. 4. the hold time for the dfme1a macro may be greater than 0 ns. use the designer 3.0 or later timer to check the hold time for thi s macro.
1- 298 act 1 timing characteristics (continued) (w orst-case commer cial conditions) input module pr opa gation dela ys C3 speed C2 speed C1 speed std speed 3.3 v speed p arameter description min. max. min. max. min. max. min. max. min. max. units t inyh p ad to y high 3.1 3.5 4.0 4.7 6.8 ns t inyl p ad to y lo w 3.1 3.5 4.0 4.7 6.8 ns input module predicted routing dela ys 1 t ird1 fo=1 routing dela y 0.9 1.1 1.2 1.4 2.0 ns t ird2 fo=2 routing dela y 1.4 1.7 1.9 2.2 3.2 ns t ird3 fo=3 routing dela y 2.1 2.5 2.8 3.3 4.8 ns t ird4 fo=4 routing dela y 3.1 3.6 4.1 4.8 7.0 ns t ird8 fo=8 routing dela y 6.6 7.7 8.7 10.2 14.8 ns global cloc k netw ork t ckh input lo w to high fo = 16 fo = 128 4.9 5.6 5.6 6.4 6.4 7.3 7.5 8.6 6.7 7.9 ns t ckl input high to lo w fo = 16 fo = 128 6.4 7.0 7.4 8.1 8.4 9.2 9.9 10.8 8.8 10.0 ns t pwh minim um pulse width high fo = 16 fo = 128 6.5 6.8 7.5 8.0 8.5 9.0 10.0 10.5 8.9 9.8 ns t pwl minim um pulse width lo w fo = 16 fo = 128 6.5 6.8 7.5 8.0 8.5 9.0 10.0 10.5 8.9 9.8 ns t cksw maxim um sk e w fo = 16 fo = 128 1.2 1.8 1.3 2.1 1.5 2.4 1.8 2.8 1.5 2.4 ns t p minim um p er iod fo = 16 fo = 128 13.2 14.2 15.4 16.7 17.6 18.9 20.9 22.3 18.2 20 ns f max maxim um f requency fo = 16 fo = 128 75 70 65 60 57 53 48 45 55 50 mhz note: 1. these parameters should be used for estimating device performance. optimization techniques may further reduce delays by 0 to 4 ns. routing delays are for typical designs across worst-case operating conditions. post- route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the devic e prior to shipment.
1- 299 act ? 1 series fpgas act 1 timing characteristics (continued) (w orst-case commer cial conditions) output module timing C3 speed C2 speed C1 speed std speed 3.3 v speed p arameter description min. max. min. max. min. max. min. max. min. max. units ttl output module timing 1 t dlh data to p ad high 6.7 7.6 8.7 10.3 15.0 ns t dhl data to p ad lo w 7.5 8.6 9.8 11.5 16.7 ns t enzh enab le p ad z to high 6.6 7.5 8.6 10.2 14.8 ns t enzl enab le p ad z to lo w 7.9 9.1 10.4 12.2 17.7 ns t enhz enab le p ad high to z 10.0 11.6 13.1 15.4 22.4 ns t enlz enab le p ad lo w to z 9.0 10.4 11.8 13.9 20.2 ns d tlh delta lo w to high 0.06 0.07 0.08 0.09 0.13 ns/pf d thl delta high to lo w 0.08 0.09 0.10 0.12 0.17 ns/pf cmos output module timing 1 t dlh data to p ad high 7.9 9.2 10.4 12.2 17.7 ns t dhl data to p ad lo w 6.4 7.2 8.2 9.8 14.2 ns t enzh enab le p ad z to high 6.0 6.9 7.9 9.2 13.4 ns t enzl enab le p ad z to lo w 8.3 9.4 10.7 12.7 18.5 ns t enhz enab le p ad high to z 10.0 11.6 13.1 15.4 22.4 ns t enlz enab le p ad lo w to z 9.0 10.4 11.8 13.9 20.2 ns d tlh delta lo w to high 0.10 0.11 0.13 0.15 0.22 ns/pf d thl delta high to lo w 0.06 0.07 0.08 0.09 0.13 ns/pf notes: 1. delays based on 35 pf loading. 2. sso information can be found in the simultaneous switching output limits for actel fpgas application note on page 4-125.
1- 300 notes: 1. nc: denotes no connection 2. all unlisted pin numbers are user i/os. 3. mode should be terminated to gnd through a 10k resistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. package pin assignments 44-pin plcc signal a1010b function A1020B function 3 vcc vcc 10 gnd gnd 14 vcc vcc 16 vcc vcc 21 gnd gnd 25 vcc vcc 32 gnd gnd 33 clk, i/o clk, i/o 34 mode mode 35 vcc vcc 36 sdi, i/o sdi, i/o 37 dclk, i/o dclk, i/o 38 pra, i/o pra, i/o 39 prb , i/o prb , i/o 43 gnd gnd 44-pin plcc 1 44 68-pin plcc signal a1010b, a10v10b function A1020B, a10v20b functions 4 vcc vcc 14 gnd gnd 15 gnd gnd 21 vcc vcc 25 vcc vcc 32 gnd gnd 38 vcc vcc 49 gnd gnd 52 clk, i/o clk, i/o 54 mode mode 55 vcc vcc 56 sdi, i/o sdi, i/o 57 dclk, i/o dclk, i/o 58 pra, i/o pra, i/o 59 prb , i/o prb , i/o 66 gnd gnd 68-pin plcc 1 68
1- 301 act ? 1 series fpgas package pin assignments (continued) 84-pin plcc signal A1020B, a10v20b function 4 vcc 12 nc 18 gnd 19 gnd 25 vcc 26 vcc 33 vcc 40 gnd 46 vcc 60 gnd 61 gnd 64 clk, i/o 66 mode 67 vcc 68 vcc 72 sdi, i/o 73 dclk, i/o 74 pra, i/o 75 prb , i/o 82 gnd notes: 1. nc: denotes no connection 2. all unlisted pin numbers are user i/os. 3. mode should be terminated to gnd through a 10k resistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. A1020B 84-pin plcc 1 84
1- 302 package pin assignments (continued) 100-pin pqfp pin a1010b function A1020B function pin a1010b function A1020B function 1 nc nc 53 nc nc 2 nc nc 54 nc nc 3 nc nc 55 nc nc 4 nc nc 56 vcc vcc 5 nc nc 63 gnd gnd 6 prb , i/o prb , i/o 69 vcc vcc 13 gnd gnd 77 nc nc 19 vcc vcc 78 nc nc 27 nc nc 79 nc nc 28 nc nc 80 nc i/o 29 nc nc 81 nc i/o 30 nc nc 82 nc i/o 31 nc i/o 86 gnd gnd 32 nc i/o 87 gnd gnd 33 nc i/o 90 clk, i/o clk, i/o 36 gnd gnd 92 mode mode 37 gnd gnd 93 vcc vcc 43 vcc vcc 94 vcc vcc 44 vcc vcc 95 nc i/o 48 nc i/o 96 nc i/o 49 nc i/o 97 nc i/o 50 nc i/o 98 sdi, i/o sdi, i/o 51 nc nc 99 dclk, i/o dclk, i/o 52 nc nc 100 pra, i/o pra, i/o notes: 1. nc: denotes no connection 2. all unlisted pin numbers are user i/os. 3. mode should be terminated to gnd through a 10k resistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. 100-pin pqfp 100 1
1- 303 act ? 1 series fpgas package pin assignments (continued) 80-pin vqfp pin a1010b, a10v10b function A1020B, a10v20b function pin a1010b, a10v10b function A1020B, a10v20b function 2 nc i/o 47 gnd gnd 3 nc i/o 50 clk, i/o clk, i/o 4 nc i/o 52 mode mode 7 gnd gnd 53 vcc vcc 13 vcc vcc 54 nc i/o 17 nc i/o 55 nc i/o 18 nc i/o 56 nc i/o 19 nc i/o 57 sdi, i/o sdi, i/o 20 vcc vcc 58 dclk, i/o dclk, i/o 27 gnd gnd 59 pra, i/o pra, i/o 33 vcc vcc 60 nc nc 41 nc i/o 61 prb , i/o prb , i/o 42 nc i/o 68 gnd gnd 43 nc i/o 74 vcc vcc notes: 1. nc: denotes no connection 2. all unlisted pin numbers are user i/os. 3. mode should be terminated to gnd through a 10k resistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. 80-pin vqfp 80 1
1- 304 package pin assignments (continued) 84-pin cpga pin a1010b function A1020B function pin a1010b function A1020B function a11 pra, i/o pra, i/o e10 vcc vcc b1 nc i/o e11 mode mode b2 nc nc f1 vcc vcc b5 vcc vcc f9 clk, i/o clk, i/o b7 gnd gnd f10 gnd gnd b10 prb , i/o prb , i/o g2 vcc vcc b11 sdi, i/o sdi,i/o g10 gnd gnd c1 nc i/o j2 nc i/o c2 nc i/o j10 nc i/o c10 dclk, i/o dclk, i/o k1 nc i/o c11 nc i/o k2 vcc vcc d10 nc i/o k5 gnd gnd d11 nc i/o k7 vcc vcc e2 gnd gnd k10 nc i/o e3 gnd gnd k11 nc i/o e9 vcc vcc l1 nc i/o notes: 1. nc: denotes no connection 2. all unlisted pin numbers are user i/os. 3. mode should be terminated to gnd through a 10k resistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. or ientation pin (c3) 84-pin cpga a b c d e f g h j k l 1 2 3 4 5 6 7 8 9 10 11
1- 305 act ? 1 series fpgas package pin assignments (continued) 84-pin cqfp pin A1020B function pin A1020B function 1 nc 53 clk, i/o 7 gnd 55 mode 8 gnd 56 vcc 14 vcc 57 vcc 15 vcc 61 sdi, i/o 22 vcc 62 dclk, i/o 29 gnd 63 pra, i/o 35 vcc 64 prb , i/o 49 gnd 71 gnd 50 gnd 77 vcc notes: 1. nc: denotes no connection 2. all unlisted pin numbers are user i/os. 3. mode should be terminated to gnd through a 10k resistor to enable actionprobe usage; otherwise it can be terminated directly to gnd. pin #1 inde x 1 84 84-pin cqfp
1- 306

▲Up To Search▲

Price & Availability of A1020B

	To Download A1020B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .